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CY22801
Universal Programmable Clock Generator (UPCG)
Features

Benefits

Integrated Phase-Locked Loop (PLL) Field Programmable Input Frequency Range: Crystal: 8 to 30 MHz CLKIN: 1 to 133 MHz LVCMOS Output Frequency: 1 to 200 MHz (Commercial Grade) 1 to 166.6 MHz (Industrial Grade) Low Jitter, High Accuracy Outputs 3.3V Operation Commercial and Industrial Temperature Ranges 8-Pin SOIC Package
Inventory of only one device, CY22801, used in various applications In-house programming of sample and prototype quantities is made available using the CY36800 InstaClock kit Input and output frequencies are customized to suit your needs High-performance PLL is tailored for multiple applications Critical timing requirements met in complex system designs Application compatibility enabled

Logic Block Diagram
XIN/CLKIN
XTAL OSC
CLKA PLL
OUTPUT DIVIDERS
CLKB CLKC
XOUT
Pin Configuration
Figure 1. CY22801 8-Pin SOIC
XIN/CLKIN VDD NC VSS 1 2 3 4 8 7 6 5 XOUT CLKC CLKA CLKB
Table 1. Pin Definition Name XIN VDD NC VSS CLKB CLKA CLKC XOUT Pin Number 1 2 3 4 5 6 7 8 Description Reference Input: Crystal or External Clock 3.3V Voltage Supply No Connect; leave this pin floating Ground Clock Output B Clock Output A Clock Output C Reference Output: Connect to external crystal. When the reference is an external clock signal (applied to pin 1), this pin is not used and must be left floating.
Cypress Semiconductor Corporation Document #: 001-15571 Rev. *B
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised June 26, 2009
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CY22801
General Description
The CY22801 is a flash-programmable clock generator that supports various applications in consumer and communications markets. The device uses a Cypress proprietary PLL to drive up to three configurable outputs in an 8-pin SOIC. The CY22801 is programmed with an easy-to-use programmer dongle, the CY36800, in conjunction with the CyClocksRTTM software. This enables fast sample generation of prototype builds for user-defined frequencies.
Output Clock Frequencies
The CY22801 is a very flexible clock generator with up to three individual outputs, generated from an integrated PLL. Details are shown in Figure 2. The output of the PLL runs at high frequency and is divided down to generate the output clocks. Two programmable dividers are available for this purpose. Thus, although the output clocks may be different frequencies, they must be related, based on the PLL frequency. It is also possible to direct the reference clock input to any of the outputs, thereby bypassing the PLL. Lastly, the reference clock may be passed through either divider. Figure 2. Basic PLL Block Diagram
REF (XIN/CLKIN) /Q PFD VCO Post Divider 1N CLKA /P Post Divider 2N
Crosspoint Switch Matrix
Field Programming the CY22801
The CY22801 is programmed using the CY36800 USB programmer dongle. The CY22801 is flash-technology based, so the parts are reprogrammed up to 100 times. This enables fast and easy design changes and product updates, and eliminates any issues with old and out-of-date inventory. Samples and small prototype quantities are programmed using the CY36800 programmer. Cypress's value added distribution partners and third party programming systems from BP Microsystems, HiLo Systems, and others, are available for large production quantities.
CLKB CLKC
CyClocksRT Software
CyClocksRT is an easy-to-use software application that enables the user to custom-configure the CY22801. Users can specify the XIN/CLKIN frequency, crystal load capacitance, and output frequencies. CyClocksRT then creates an industry standard JEDEC file, which is used to program the CY22801. When needed, an advanced mode is available that enables users to override the automatically generated VCO frequency and output divider values. CyClocksRT is a component of the CyberClocksTM software, which is downloaded free of charge from the Cypress website at http://www.cypress.com.
Reference Crystal Input
The input crystal oscillator of the CY22801 is an important feature because of the flexibility it allows the user in selecting a crystal as a reference clock source. The oscillator inverter has programmable gain, enabling maximum compatibility with a reference crystal, based on manufacturer, process, performance, and quality. Input load capacitors are placed on the CY22801 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when nonlinear load capacitance is affected by load, bias, supply, and temperature changes. The value of the input load capacitors is determined by eight bits in a programmable register. Total load capacitance is determined by the formula: CapLoad = (CL - CBRD - CCHIP)/0.09375 pF In CyClocksRT, enter the crystal capacitance (CL). The value of CapLoad is determined automatically and programmed into the CY22801.
CY36800 InstaClockTM Kit
The Cypress CY36800 InstaClock Kit comes with everything needed to design the CY22801 and program samples and small prototype quantities. The CyClocksRT software is used to quickly create a JEDEC programming file, which is then downloaded directly to the portable programmer that is included in the CY36800 InstaClock Kit. The JEDEC file can also be saved for use in a production programming system for larger volumes. The CY36800 also comes with five samples of the CY22800, which are programmed with preconfigured JEDEC files using the InstaClock software.
Applications
Controlling Jitter
Jitter is defined in many ways, including:

Phase noise Long-term jitter Cycle-to-cycle jitter Period jitter Absolute jitter Deterministic jitter
Document #: 001-15571 Rev. *B
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CY22801
These jitter terms are usually given in terms of RMS, peak-to-peak, or in the case of phase noise, dBC/Hz with respect to the fundamental frequency. Actual jitter is dependent on

Reducing capacitive clock output loading to a minimum lowers current spikes on the clock edges and thus reduces jitter. Reducing the total number of active outputs also reduces jitter in a linear fashion. However, it is better to use two outputs to drive two loads than one output to drive two loads. For additional information, refer to the application note, Jitter in PLL-based Systems: Causes, Effects, and Solutions, available at http://www.cypress.com.
XIN jitter and edge rate Number of active outputs Output frequencies Supply voltage Temperature Output load
Cypress Programmable Clocks
Cypress offers a wide range of programmable clock synthesizers that can generate any other frequencies not covered by the CY22801. Table 2 summarizes all Cypress programmable devices including CY22801.
Power supply noise and clock output loading are two major system sources of clock jitter. Power supply noise is mitigated by proper power supply decoupling (0.1-F ceramic cap) of the clock and ensuring a low impedance ground to the chip. Table 2. Cypress Programmable Clocks[1] Part # CY22800 CY22801 CY22050 CY22150 CY25100 CY25200 CY241V08 CY22392 CY22381 CY22393 CY22394/5 CY22388/89/91 No. of PLL 1 1 1 1 1 1 1 3 3 3 3 4 Input Freq. 0.5-100 1-133 1-133 1-133 8-166 3-166 27/13.5 1-166 1-166 1-166 1-166 1-100 Output Freq. 1-200 1-200 0.08-200 0.08-200 3-200 3-200 27/13.5 1-200 1-200 1-200 1-200 4.2-166
Package 8-SOIC 8-SOIC 16-TSSOP 16-TSSOP 8-SOIC/TSSOP 16-TSSOP 8-SOIC 16-TSSOP 8-SOIC 16-TSSOP 16-TSSOP 16/20-TSSOP, 32-QFN
No. of Outputs Up to 3 Up to 3 Up to 6 Up to 6 Up to 2 Up to 6 Up to 2 Up to 6 Up to 3 Up to 6 Up to 5 Up to 8
Spread Spectrum Yes No No No Yes Yes No No No No No No
VCXO Yes No No No No No Yes No No No No Yes
I2C No No No Yes No No No No No Yes No No
Note 1. The CY22800 and CY22801 are programmed using the programming dongle included in the CY36800 InstaClock Kit. The CY3672 programmer are used to program all other Cypress Programmable Clocks.
Document #: 001-15571 Rev. *B
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CY22801
Absolute Maximum Conditions
Parameter VDD TS TJ VIO ESD Supply Voltage Storage Temperature Junction Temperature Input and Output Voltage Electro-Static Discharge Voltage per MIL-STD-833, Method 3015 Description Min -0.5 -65 - VSS - 0.5 2000 Max 4.6 150 125 VDD + 0.5 - Unit V C C V V
Recommended Operating Conditions
Parameter VDD TA CLOAD tPU Operating Voltage Ambient Temperature, Commercial Grade Ambient Temperature, Industrial Grade Max. Load Capacitance on the CLK output Power up time for VDD to reach minimum specified voltage (power ramps must be monotonic) Description Min 3.14 0 -40 - 0.05 Typ 3.3 - -- - Max 3.47 70 85 15 500 Unit V C C pF ms
Recommended Crystal Specifications
Parameter FNOM CLNOM R1 DL Name Nominal Crystal Frequency Nominal Load Capacitance Equivalent Series Resistance Fundamental mode (ESR) Crystal Drive Level No external series resistor assumed Description Parallel resonance, fundamental mode, and AT cut Min 8 6 - - Typ - - 35 0.5 Max 30 30 50 2 Unit MHz pF mW
DC Electrical Specifications[2]
Parameter IOH IOL VIH VIL CIN1 CIN2 IDD[3, 4] Name Output High Current Output Low Current Input High Voltage Input Low Voltage Input Capacitance Input Capacitance VDD Supply Current All input pins except XIN and XOUT XIN and XOUT pins Description VOH = VDD - 0.5, VDD = 3.3V (source) VOL = 0.5, VDD = 3.3V (sink) Min 12 12 0.7*VDD VSS - 0.3 - - - Typ 24 24 - - - 24 70 Max - - VDD + 0.3 0.3*VDD 7 - - Unit mA mA V V pF pF mA
Notes 2. Not 100% tested, guaranteed by design. 3. IDD current specified for three CLK outputs running at 100 MHz. 4. Use CyClocksRT to calculate actual IDD for specific output frequency configurations.
Document #: 001-15571 Rev. *B
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CY22801
AC Electrical Characteristics[2]
Parameter fREFC fREFD fOUT Name Reference Frequency crystal Reference Frequency - driven Output Frequency, Commercial Grade Output Frequency, Industrial Grade DC t3 t4 t5[5] t6[6] t10 Output Duty Cycle Output Rising Edge Slew Rate Output Falling Edge Slew Rate Skew Clock Jitter PLL Lock Time Duty Cycle is defined in Figure 4, 50% of VDD 20% - 80% of VDD 80% - 20% of VDD Output-output skew between related outputs Peak-to-peak period jitter Description Min 8 1 1 1 45 0.8 0.8 - - - Typ - - - - 50 1.4 1.4 - 250 - Max 30 133 200 166.6 55 - - 250 - 3 Unit MHz MHz MHz MHz % V/ns V/ns ps ps ms
Test Circuit
Figure 3. Test Circuit Diagram VDD 0.1F OUTPUTS CLKout CLOAD
Timing Definitions
Figure 4. Duty Cycle Definition; DC = t2/t1 t1 t2 CLK 50% 50%
GND
Figure 5. Rise and Fall Time Definitions t3 80% CLK 20% t4
Notes 5. Skew value guaranteed when outputs are generated from the same divider bank. 6. Jitter measurement may vary. Actual jitter is dependent on input jitter and edge rate, number of active outputs, input and output frequencies, supply voltage, temperature, and output load. For more information, refer to the application note, Jitter in PLL-based Systems: Causes, Effects, and Solutions.
Document #: 001-15571 Rev. *B
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CY22801
Ordering Information
Ordering Code CY22801FXC
[7]
Package Type 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC-Tape and Reel 8-Pin SOIC 8-Pin SOIC-Tape and Reel 8-Pin SOIC 8-Pin SOIC-Tape and Reel
Operating Range Commercial, 0C to 70C Industrial, - 40C to 85C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Industrial, - 40C to 85C Industrial, - 40C to 85C Commercial, 0C to 70C Commercial, 0C to 70C Industrial, - 40C to 85C Industrial, - 40C to 85C
Operating Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
CY22801FXI[7] CY22801SXC-xxx[7, 8] CY22801SXC-xxxT[7, 8] CY22801KFXC CY22801KFXCT CY22801KFXI CY22801KFXIT CY22801KSXC-XXX
[8]
8-Pin SOIC 8-Pin SOIC-Tape and Reel 8-Pin SOIC 8-Pin SOIC-Tape and Reel
CY22801KSXC-XXXT[8] CY22801KSXI-xxx[8] CY22801KSXI-xxxT[8]
Package Diagram
Figure 6. 8-Pin (150-Mil) SOIC SZ08
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012
0.230[5.842] 0.244[6.197]
0.150[3.810] 0.157[3.987]
4. PACKAGE WEIGHT 0.07gms
PART # S08.15 STANDARD PKG. 5 8 SZ08.15 LEAD FREE PKG.
0.189[4.800] 0.196[4.978]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249]
0.0138[0.350] 0.0192[0.487]
51-85066-*C
Notes 7. Not recommended for new designs. 8. Ordering codes with "xxx" are factory-programmed configurations. Factory programming is available for high volume orders. For more details, contact your local Cypress field application engineer or Cypress sales representative.
Document #: 001-15571 Rev. *B
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CY22801
Document History Page
Document Title: CY22801 Universal Programmable Clock Generator (UPCG) Document Number: 001-15571 REV. ** *A ECN NO. 1058080 2440787 Orig. of Change KVM/ KKVTMP AESA Submission Date 05/10/07 05/16/08 New data sheet Updated template. Added Note 7 and 8. Added existing part numbers CY22801FXCT, CY22801FXI, CY22801FXIT, CY22801SXC-xxx and CY22801SXC-xxxT in ordering information table. Added new part numbers CY22801KFXC, CY22801KFXCT, CY22801KFXI, CY22801KFXIT, CY22801KSXC-XXX and CY22801KSXC-XXXT. Add Industrial Grade Ambient Temperature to Recommended Operating Conditions. Add separate Fout max limit for industrial temp. Add temperature ranges to the Ordering Information Table. Remove CY22801FXCT and CY22801FXIT from Ordering Information Table. Add CY22801KSXI-xxx and CY22801KSXI-xxxT to Ordering Information Table. Correct package reference from S8 to SZ08. Description of Change
*B
2724806
KVM/ AESA
6/26/09
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
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(c) Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-15571 Rev. *B
Revised March 12, 2009
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CyClocksRT, CyberClocks, and InstaClock are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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